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PRELIMINARY
VES9600
SINGLE CHIP DVB-T CHANNEL RECEIVER
FEATURES
* 2K and 8K COFDM demodulator ( Fully DVB-T compliant : ETS 300-744). * All modes supported including hierarchical modes. * On chip 9-bit ADC. * Digital down conversion. * Fully automatic transmission parameters detection. * Crystal or VCXO clock generation. * Frequency offset estimator to speed up the scan. * RF Tuner input power measurement * On chip FEC decoder, full DVB-T compliant. * Parallel or serial transport stream interface. * DSP based synchronization. * BER measurement * SNR estimation * Channel frequency response output. * Channel impulse response output. * Controllable dedicated I2C tuner bus. * 2 low frequency spare DAC. () * Spare I/O. * I2C bus interface, for easy control. * CMOS 0.35m technology.
DESCRIPTION
The VES9600 is a single chip channel receiver for 2K and 8K COFDM modulated signals based on the ETSI specification (ETSI 300 744). The device interfaces directly to an IF signal, which is sampled by a 9-bit AD converter. The VES9600 performs all the COFDM demodulation tasks from IF signal to the MPEG2 transport stream. An internal DSP core manages the synchronization and the control of the demodulation process. After base band conversion and FFT, the channel frequency response is estimated based on the scattered pilots, and filtered in both time and frequency domains. This estimation is used as a correction on the signal, carrier by carrier. A common phase error and estimator is used to deal with the tuner phase noise. The FEC decoder is automatically synchronized thanks to the frame synchronization algorithm that uses the TPS information included in the modulation. Finally descrambling according to DVB-T standard, is achieved at the Reed Solomon output. This device is controlled via an I2C bus. The chip provides a switchable tuner I2C bus to be disconnected from the I2C master when not necessary. The DSP software code can be fed to the chip via the master I2C bus or via a dedicated I2C bus (Eeprom). Designed in 0.35 m CMOS technology and housed in a 208-pin MQFP package, the VES9600 operates over the commercial temperature range.
APPLICATIONS
* DVB-T fully compatible. * Digital data transmission using COFDM modulations.
VLSI/comatlas reserves the right to make any change at anytime without notice.
VES 9600 rev 1.2 / Sep 99
CAUTION
This document is preliminary and is subject to change. Contact a VLSI Technology representative to determine if this is the current information on this device.
The information contained in this document has been carefully checked and is believed to be reliable. However, VLSI Technology makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon, it. VLSI Technology does not guarantee that the use of any information contained herein will not infringe upon the patent, trademark, copyright, mask work right or other rights of third parties, and no patent or other license is implied hereby. This document does not in any way extend VLSI Technology warranty on any product beyond that set forth in its standard terms and conditions of sale. VLSI Technology reserves the right to make changes in the products or specifications, or both, presented in this publication at any time and without notice. LIFE SUPPORT APPLICATIONS : VLSI Technology products are not intended for use as critical components in life support appliances, devices, or systems in which the failure of a VLSI Technology product to perform could be expected to result in personal injury.
VES9600 Data sheet revision history
Revision number Rev1.0 Rev1.1 Rev1.2 Observation Engineering document Typo errors Pin 7, 17, 70 & 200 from VCC to VDD
VLSI/comatlas reserves the right to make any change at anytime without notice.
VES 9600 rev 1.2 / Oct 99 / p2
General purpose OAK+ DSP CORE (XIN MIPS) Frequency Timing framing recovery 10 / 3 digital inputs/outputs analog outputs
NCO CHANNEL ESTIMATOR TIMING
FREQUENCY
INTERPOLATOR
CONFIDENCE
CPE
IF
CONVERSION RECOVERY DELAY LINE FFT
9 CARRIER
BASE-BAND
3 Symbols
CORRECTION
I RECOV_DATA Q
FIGURE 1 : FUNCTIONAL BLOCK DIAGRAM
ADC
SACLK
XIN INNER
/ AGC
/2
VITERBI DECODER
VLSI/comatlas reserves the right to make any change at anytime without notice.
DE-INTERLEAVER OUTER DE-INTERLEAVER R. S. DECODER DE-SCRAMBLER DO OCLK DEN
TO AGC
SDA
2 IC
SCL
INTERFACE
VES 9600 rev 1.2 / Oct 99 / p3
TO TUNER
INPUT - OUTPUT SIGNAL DESCRIPTION
SYMBOL CLR# XIN XOUT SACLK USE_NCO CTRL_VCXO CLK_X1 CLK_X2 9 25 33 26 181 180 PIN NUMBER 32 8 TYPE DESCRIPTION CLOCK AND RESET SIGNALS I reset signal, active low Crystal oscillator input pin. When USE_NCO pin is high a third overtone XTAL should be connected between the XIN and XOUT pins. I When USE_NCO pin is low a VCXO should be connected between XIN and via a RC filter to the CTRL_VCXO output. O Crystal oscillator output pin. O Sampling frequency output. This output clock can be fed to an (5V) external (10-bit) ADC as sampling clock. SACLK= XIN/2 I When low the chip is in VCXO mode else in NCO mode O If not in NCO mode, control of an external sampling VCXO (after low(5V) pass filtering) O Internal SACLK equivalent monitoring output. (5V) O Internal SACLK* 2 equivalent monitoring output. (5V) DEMODULATOR SIGNALS Input data from an external ADC, FI must be tied to ground when not used, positive notation (from 0 to 1023) or two's complement notation (from -512 to 511). to be connected to FFT_WIN_OUT in default mode. Output signal, indicating the start of the active data; equals 1 during complex sample 0 of the active FFT block output value from the Delta-Sigma Modulator, used to control a logscaled amplifier (after analog filtering ) Demodulator output signal (after channel correction), synchronous with the falling edge of CLK_X1, provided in a multiplexed way, I first. Normal order. Multiplexed output bearing the confidence factor during I and channel response square amplitude during Q (4 MSB bits), respectively to RECOV_DATA. (For the channel square amplitude see C2_H2) 4 LSB bits of the channel response square amplitude according to CFND. enable clk18 to synchronize and phase the RECOV_DATA H2 et CFND outputs. EN_CLK is set to 1 during I and 0 during Q. Output signal, indicating the start of the active data out of the equalizer; equals 1 during sample Kmin of the RECOV_DATA current output block, for 2 18MHz clock cycles. CAUTION : sample Kmin does not convey regular data, since it happens to be a continual carrier; it is the first active (non zero) sample of the current OFDM block, but D_VAL and TPS_VAL (see below) will be low. active when RECOV_DATA corresponds to regular data . Indicate the active data out of the first block in a frame at the demodulation part output. (RECOV_DATA) Same as FRAME in 8K; in 2K, active only on the first block of each superframe. Indicates the beginning of a new SUPER-FRAME. active when RECOV_DATA corresponds to TPS demodulated data . front end lock. FEL is an output drain output and therefore requires an external pull up resistor. VES 9600 rev 1.2 / Oct 99 / p4
FI[9:0]
12-13-14-15-1619-20-21-22-23 81 82 27 168-169-170171-172-173174-175 151-152-153-154
I
FFT_WIN_IN FFT_WIN_OUT VAGC RECOV_DATA [7:0] CFND[3 :0]
I O (3.3) O (5V) O (3.3) O (3.3) O (3.3) O (3.3) O (3.3)
H2[3:0] EN_CLK D_START
160-161-162-163 150 145
D_VAL FRAME SUPER_FRAME TPS_VAL FEL
144 147 146 143 77
O (3.3) O (3.3) O (3.3) O (3.3) 0 (5V)
VLSI/comatlas reserves the right to make any change at anytime without notice.
76 IT
O (5V)
Interrupt line. This output interrupt line can be configured by the I2C interface. See registers Itsel and Itstat. IT is an open drain output and therefore requires an external pull up resistor. FEC OUTPUTS output data carrying the current sample of the current MPEG2 packet (188 bytes), delivered on the rising edge of OCLK by default. When the serial mode is selected, the output data is delivered by DO[0]. Output CLock. OCLK is the output clock for the parallel DO[7:0] outputs. OCLK is internally generated depending on which interface is selected. output data validation signal active high during the valid and regular data bytes (may be inverted, see serial bus description). Pulse SYNChro. This output signal goes high on a rising edge of OCLK when a synchro byte is provided, then goes low until the next synchro byte (may be inverted). RS error flag, active high on one RS packet if the RS decoder fails in correcting the errors (may be inverted). Frame start active high for one OCLK output clock cycle at the beginning of a new superframe made of 272 OFDM symbols for the 2k mode and made of 68 OFDM symbols for the 8k mode (may be inverted as C3_psync). viterbi output data stream, delivered on the rising hedge of HVIT. You can also find the viterbi output on DO[0] after by-passing the RS and the descrambling. viterbi output data stream clock, according to DVIT. ON-CHIP ADC SIGNALS Negative input to the A/D converter. This pin is DC biased to half supply through an internal resistor divider (2x10K resistors). In order to remain in the range of the ADC, the voltage difference between pins VIP and VIM should be between -0.5 and 0.5 volts. Positive input to the A/D converter. This pin is DC biased to half supply through an internal resistor divider (2x10K resistors). In order to remain in the range of the ADC, the voltage difference between pins VIP and VIM should be between -0.5 and 0.5 volts. This pin is connected to a tap point on an internal resistor divider used to create CMO and CMI. An external capacitor of value 0.1f should be connected between this point and ground to provide good power supply rejection from the positive supply at higher frequencies. An external resistor of value 3.3k should be connected between this pin and ground to provide good accurate bias currents for the analog circuits on the ADC. This pin provides the common-mode in voltage for the analog circuits on the ADC. It is the buffered version of a voltage derived from an onchip resistor devider, and has a nominal value of 0.75 x VD3. This pin provides the common-mode out voltage for the analog circuits on the ADC. It is the buffered version of a voltage derived from an onchip resistor devider, and has a nominal value of 0.5 x VD3. This is the output of an on-chip resistor divider. An external capacitor of value 0.1f should be connected between this point and ground to provide good power supply rejection from the positive supply at higher frequencies. Reference voltages VREFP and VREFM are derived from the voltage on VREF. This is a positive voltage reference for the A/D converter. It is derived VES 9600 rev 1.2 / Oct 99 / p5
DO[7:0]
OCLK
118-119-120121-124-125126-127 113
O (3.3) O (3.3) O (3.3) O (3.3) O (3.3) O (3.3)
DEN PSYNC
115 112
UNCOR FSTART
114 109
108 DVIT HVIT 107
O (3.3) O (3.3)
48 VIM 49 VIP 42 CMCAP 39 RBIAS 40 CMI 41 CMO 45 VREF O O O I I I I
VREFP
44
O
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43 VREFM VD1 VS1 VD2 VS2 VD3 VS3 VD4 VS4 38 37 51 50 46 47 52 36 O I I I I I I I I
from the voltage on pin VREF through an on-chip fully-differential amplifier. The voltage on this pin is nominally equal to CMO + 0.25 volts. This is the negative voltage reference for the A/D converter. It is derived from the voltage on pin VREF through an on-chip fullydifferential amplifier. The voltage on this pin is nominally equal to CMO- 0.25 volts. Power supply input for the digital switching circuitry (3.3 typ). Ground return for the digital switching circuitry. Power supply input for the analog clock drivers (3.3V typ). Ground return for the analog clock drivers. Power supply input for the analog circuits (3.3V typ). Ground return for analog circuits. Power supply input that connects to an n-well guard ring that surrounds the ADC (3.3V typ). Ground return for the well guard ring that surrounds the ADC. I2C INTERFACES I2C serial clock. Up to 700 kbit/s, in this functional mode, I2C slave device I2C serial data inout, open drain I/O pad Up to 700 kbit/s, in this functional mode, I2C slave device SADDR[1:0] are the 2 LSBs of the I2C address of the VES9600. The MSBs are internally set to 00010. Therefore the complete I2C address of the VES9600 is (MSB to LSB): 0,0,0,1,0,SADDR[1], SADDR[0] tuner I2C serial clock signal. Can be connected or not to the master I2C bus. (open drain) Tuner I2C data bus. Can be connected or not to the master I2C bus. (open drain) Extra I2C clock line to download DSP code from an external EEPROM. Optional mode. Can be connected to the master I2C Bus , (open drain) Extra I2C data bus to download DSP code from an external EEPROM. Optional mode. Can be connected to the master I2C Bus. (open drain) EEPRAD[1:0] are the 2 LSBs of the I2C address of the EEPROM in mode boot alone. The MSBs are internally set to 00010. Therefore the complete I2C address of the EEPROM is (MSB to LSB): 1,0,1,0,0,EEPADDR[1], EEPADDR[0] I2C EEPROM bus speed (SCL_EEP) : 0 : 800Khz; 1 : 400Khz; 2 : 200Khz; 3 : 100Khz. DSP SIGNALS processor control, Boot Mode If 0 the DSP download its software from an external eeprom on the dedicated I2C BUS SDA_EEP and SCL_EEP. If 1 the software is downloaded via a host in the I2C register CODE_IN. In this case no need of an external eeprom. Boot on the bist mode to test the DSP RAM bank. If good SP_OUT[0] = 1 In normal mode of operation, DSP_BIST must be grounded. Oak+ DSP smart debug interface, SDI+ external JTAG clock Oak+ DSP smart debug interface, SDI+ JTAG serial output Oak+ DSP smart debug interface, SDI+ JTAG test mode select Oak+ DSP smart debug interface, SDI+ JTAG serial output VES 9600 rev 1.2 / Oct 99 / p6
SCL SDA
62 63 206-207
I I/O
SADDR[1:0] SCL_TUN SDA_TUN SCL_EEP 64 65 66
I O I/O O
SDA_EEP
67
I/O
204-205 EEPADDR[1:0] 202-203 I
EEPSP[1:0]
I
DOWNLOAD_M ODE
4
I
3 DSP_BIST SDI_TCK SDI_TDI SDI_TMS SDI_TDO 194 195 196 197 I I I I O
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SP_IN[3:0] SP_OUT[7:0] CTRL[1:0] DS_SPARE_1
72-73-74-75 88-89-90-91-9293-94-95 84-85 28
(3.3) I O (3.3) O (3.3) O (5V) O (5V) I
Spare inputs Spare outputs control detection signal, flag monitoring outputs. Spare delta-sigma output. Managed by the DSP to handle a low frequency DAC. ( automatic first stage tuner AGC measurement for example). Spare delta-sigma output. Managed by the DSP or by an I2C register to generate an analog level. (after a RC low-pass filter) Must be set to "1" BOUNDARY SCAN clock signal for boundary-scan. Wired to GND (if not used) Input port for boundary-scan. Wired to GND (if not used) Mode programming signal for boundary-scan. Wired to GND (if not used) Asynchronous reset signal for boundary-scan. Wired to GND (if not used) Output port for boundary-scan. NC (if not used) POWER SUPPLIES
DS_SPARE_2 TESTADC
29 55
TCK TDI TMS TRST TDO
187 188 190 189 191
I I I I O (5V)
GND
VCC VDD
GN 2-10-18-31-6971-80-87-97117-123-134142-149-165177-183-193-201 1-30-68-79-192 VCC 5V 7-17-70-86-96- VDD 3.3V 116-122-133141-148-164176-182-200
Ground level 0 V
Positive Power Supply 5 V typical
Positive Power Supply 3.3 V typical
FIGURE 2 : BLOCK DIAGRAM
VDD GND VCC VDi VSi 4 4 RECOV_DATA 24 MONITORING SACLK VAGC SDA_TUN SCL_TUN IT FEL PSYNC UNCOR DEN OCLK DO[7:0]
XIN
XOUT
POWER SUPPLIES
FI[9:0] CLR# VIP VIM
10 INPUTS
VES9600
OUTPUTS
8 INTERFACE DSP_INTERFACE JTAG
3 SADDR[1:0] SCL SDA
3 SDA_EEP SDI_TDO
4 TDO
VLSI/comatlas reserves the right to make any change at anytime without notice.
VES 9600 rev 1.2 / Oct 99 / p7
FIGURE 3 : PIN DIAGRAM
VSS VDD RECOV_DATA[0]
RECOV_DATA[1] RECOV_DATA[2]
RECOV_DATA[3] RECOV_DATA[4] RECOV_DATA[5]
208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157
VCC VSS DSP_BIST DOWNLOAD_MODE VDD XIN XOUT VSS FI[9] FI[8] FI[7] FI[6] FI[5] VDD VSS FI[4] FI[3] FI[2] FI[1] FI[0] SACLK CTRL_VCXO VAGC DS_SPARE_1 DS_SPARE_2 VCC VSS CLB# USE_NCO VS4 VS1 VD1 RBIAS CMI CMO CMCAP VREFM VREFP VREF VD3 VS3 VIM VIP VS2 VD2 VD4
RECOV_DATA[6] RECOV_DATA[7] VSS VDD H2[0] H2[1] H2[2] H2[3] -
SADDR[0] SADDR[1] EEPRAD[0]
EEPRAD[1] EEPSPD[0]
EEPSPD[1] VSS VDD SDI_TDO SDI_TMS
SDI_TDI SDI_TCK VSS VCC TDO TMS
VSS VDD CLK_X1 CLK_X2
TRST TDI TCK
-
-
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134
CFND[0] CFND[1] CFND[2] CFND[3] EN_CLK VSS VDD FRAME SUPER_FRAME D_START D_VAL TPS_VAL VSS VDD VSS VDD DO[0] DO[1] DO[2] DO[3] VSS VDD DO[4] DO[5] DO[6] DO[7] VSS VDD DEN UNCOR OCLK PSYNC FSTART DVIT HVIT -
VES9600
133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
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TEST_ADC
IT SP_IN[0] SP_IN[1] SP_IN[2] SP_IN[3] VSS VDD VSS VCC SDA_EEP SCL_EEP SDA_TUN SCL_TUN SDA SCL
VSS VCC FEL
SP_OUT[3] SP_OUT[4] SP_OUT[5] SP_OUT[6] SP_OUT[7] VSS VDD CTRL[0] CTRL[1] FFT_WIN_OUT FFT_WIN_IN
SP_OUT[1] SP_OUT[2]
VES 9600 rev 1.2 / Oct 99 / p8
VSS VDD SP_OUT[0]
TABLE 1 : PIN DESCRIPTION
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Pin Name VCC VSS DSP_BIST
DWNLD_MODE
VCC XIN XOUT VSS FI[9] FI[8] FI[7] FI[6] FI[5] VCC VSS FI[4] FI[3] FI[2] FI[1] FI[0] SACLK
CTRL_VCXO
VAGC
DS_SPARE_1 DS_SPARE_2
VCC VSS CLR# USE_NCO VS4 VS1 VD1 RBIAS CMI CMO CMCAP VREFM VREFP VREF VD3 VS3 VIM VIP VS2 VD2 VD4 -
Direction I I 3 I 3 I I O 3 I I I I I I I I I I I 3 I O O O O O I I 3 I 3 I I O O I O O O I I -
54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108
TEST_ADC SCL SDA SCL_TUN SDA_TUN SCL_EEP SDA_EEP VCC VSS VCC VSS SP_IN[3] SP_IN[2] SP_IN[1] SP_IN[0] IT FEL VCC VSS
FFT_WIN_IN
FFT_WIN_OUT
CTRL[1] CTRL[0] VDD VSS SP_OUT[7] SP_OUT[6] SP_OUT[5] SP_OUT[4] SP_OUT[3] SP_OUT[2] SP_OUT[1] SP_OUT[0] VDD VSS HCORE DCORE
I 3 I 3 O 3 O 3 O 3 O 3 O I I/O OD I/O OD I/O I I I I OD OD 3 I 1 I O 3 I O O O O O O O O O O 3 I 3 I 3 I 3 I 3 I 3 I 3 I 3 I 3 I O O
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163
FSTART PSYNC OCLK UNCOR DEN VDD VSS DO[7] DO[6] DO[7] DO[4] VDD VSS DO[3] DO[2] DO[1] DO[0] VDD VSS VDD VSS TPS_VAL D_VAL D_START
SUPER_FRAME
FRAME VDD VSS EN_CLK CFND[3] CFND[2] CFND[1] CFND[0] H2[3] H2[2] H2[1] H2[0]
O 3 O 3 I O O O O O O O O O O O O 3 I 3 I 3 I 3 I 3 O 3 O 3 O 3 I 3 I 3 I 3 I O O O O O O O O O O 3 I 3 I 3 I 3 I O O O O
VLSI/comatlas reserves the right to make any change at anytime without notice.
VES 9600 rev 1.2 / Oct 99 / p9
164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180
VDD VSS RECOV_DATA[7] RECOV_DATA[6] RECOV_DATA[5] RECOV_DATA[4] RECOV_DATA[3] RECOV_DATA[2] RECOV_DATA[1] RECOV_DATA[0]
VDD VSS CLK_X2
3 O 3 I O O O O O O O O 3 O 3 I O
181 182 183 184 185 186 187 188 189 190 191 192 193 194 95 196 197
CLK_X1 VDD VSS TCK TDI TRST TMS TDO VCC VSS SDI_TCK SDI_TDI SDI_TMS SDI_TDO
O 3 O 3 O I I I I OD I I I OD
198 199 200 201 202 203 204 205 206 207 208
VCC VSS EEPSPD[1] EEPSPD[0] EEPRAD[1] EEPRAD[0] SADDR[1] SADDR[0] -
O 3 O I I I I I I 3 I
3
Notes : 1.All inputs (I) are TTL, 5V tolerant inputs (excepted FFT_WIN_IN which is 3.3V only) 2.OD are Open Drain 5V outputs, so they must be connected to a pull-up resistor to either VDD or VCC 3. Test IO, inputs must be connected to GND.
VLSI/comatlas reserves the right to make any change at anytime without notice. VES 9600 rev 1.2 / Oct 99 / p10
PACKAGE INFORMATION
NOTE : Dimensions are in millimeters
VLSI/comatlas reserves the right to make any change at anytime without notice. VES 9600 rev 1.2 / Oct 99 / p11

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